Event

Workshop

 

​When

13:30 - 18:00

 

Where

Room 5C

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Abstract

Classifiers such as Neural Networks have become ubiquitous solutions when complex classification tasks are at stake, while hybridization and CMOS processing capabilities have paved the way towards fully integrated sensors. Not surprisingly, the convergence of the two worlds in now on but poses complex challenges: among them compactness, low power consumption and high classification ratio. This workshop aims at proving an overview of the challenges of integrated NN design, technological solutions and use cases.

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Organisers

Antoine Dupret (CEA-Leti, FR), Cedric Tubert (STMicroelectronics, FR)

Antoine Dupret is currently working on image sensors and compact Neural Networks at the Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA), France. In 1996 he was appointed Assistant Professor with the Université de Paris 13, then Full Professor at ESIEE Engineering in 2009. He joined CEA in 2010 as senior expert in Image Sensors. He was Head of the Sensor Integration and Reliability Lab. He earned a master's and doctoral degree in electrical engineering from the Ecole Normale Supérieure de Cachan and Université de Paris Sud 11, France in 1991 and 1995, respectively.

 

Cedric Tubert – System & sensor architect – Analogue and Mixed Signal Group / Imaging Division – STMicroelectronics.

After earning his Ph.D. in 2010 in the field of indirect Time-of-Flight cameras based on pinned-photodiode pixels, Cedric TUBERT joined ST as a design engineer and then architect working on CMOS image sensor analogue and mixed design. Today, Cedric is a Principal Senior Member of ST's Technical Staff focusing on indirect Time-of-Flight system architecture including pixel, sensor, algorithm/ISP, RX & TX optics specifications. Cedric TUBERT received the best joint paper awards from ESSCIRC/ESSDERC 2021 in Grenoble for “Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera”

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Program

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13:30 - 14:10

Algorithm-Architecture co-design for highly constrained, application-oriented deep learning models

William Guicquero (CEA-Leti, FR)

 

14:10 - 14:50

Accelerate Gated Recurrent Neural Networks with Neuromorphic Principles

Chang Gao (TU Delft, NL)

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14:50 - 15:30

Integrated Neural Networks, the challenge of featuring versatility and compactness

Dennis Sylvester (University of Michigan, US)

 

15:30 - 16:00

Coffee Break 

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16:00 - 16:40

Opportunities and challenges of AI integration in image sensors

Jérôme Chossat (STMicroelectronics, FR)

 

16:40 - 17:20

Computing at the extreme edge – running programs inside pixels

Piotr Dudek (University of Manchester, GB)

 

17:20 - 18:00

In-memory Computing for Sensor-rich Edge Platforms

Naveen Verma (Princeton University, US)

 

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Biosketches

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William Guicquero received the M.Sc. degree in applied mathematics from the Grenoble Institute of Technology (ENSIMAG), France, and the Ph.D. degree in microelectronics and signal processing from the Swiss Federal Institute of Technology (EPFL), Switzerland. Since 2014, he has been working at the CEA-LETI as a research engineer in the field of image sensor design. He has been involved in various industrial & academic research activities related to data compression, image rendering, sensor characterization and machine learning. His scientific research focuses on algorithm-architecture co-design for imaging technologies.

 

Chang Gao is an Assistant Professor at the Department of Microelectronics, TU Delft. His research interest is designing energy-efficient digital AI hardware for edge computing. He is also an enthusiast of neuromorphic computing. He aims to bridge the gap between artificial neural networks (ANNs) and spiking neural networks (SNNs) by applying brain-inspired neuromorphic principles to accelerate deep neural network (DNN) architectures while maintaining competitive accuracy on real-world tasks. He receives the 2022 Mahowald Early Career Award for Neuromorphic Engineering and the 2023 MIT Technology Review European Innovators Under 35 for his contribution to designing hardware and software to realize massive speedup of RNN computing.

 

Jérôme Chossat is director of the digital architecture department and technical fellow in the Imaging Division of STMicroelectronics. In this role, he is responsible for roadmap and execution of IP and Soc digital architectures, embedded Software, Image Signal Processing and Computer Vision solutions, from early architecture to product implementation.
Jérôme obtained an engineering degree in Electronics from the ENSEIRB (Ecole Nationale Superieur d’Electronique et Informatique de Bordeaux) in 1993 and an M.phil. degree from Bordeaux Univ in Microelectronics on the same year.
He has been working for STMicroelectronics since 1996 when he joined a team designing image processors for television and webcams. He has been involved since the early beginning of mobile phone imaging, in the development of families of image signal processors for mobile phone applications and directly contributed to very high-volume mobile phone camera systems.
His current research interests are around ultra-low power imaging and Artificial intelligence integration in image sensors.